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SDSPI fix for ESP32-C5: correct API v5.5, CMake dependencies, pin mapping

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Clawdia
2026-05-09 17:59:43 +02:00
parent 240a374148
commit 913b33d839
1519 changed files with 210337 additions and 610 deletions
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v2x_fw/build/bootloader/config/kconfig_menus.json
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v2x_fw/build/bootloader/config/sdkconfig.cmake
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v2x_fw/build/bootloader/config/sdkconfig.h
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/*
* Automatically generated file. DO NOT EDIT.
* Espressif IoT Development Framework (ESP-IDF) 5.5.1 Configuration Header
*/
#pragma once
#define CONFIG_SOC_ADC_SUPPORTED 1
#define CONFIG_SOC_ANA_CMPR_SUPPORTED 1
#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1
#define CONFIG_SOC_UART_SUPPORTED 1
#define CONFIG_SOC_UHCI_SUPPORTED 1
#define CONFIG_SOC_GDMA_SUPPORTED 1
#define CONFIG_SOC_AHB_GDMA_SUPPORTED 1
#define CONFIG_SOC_GPTIMER_SUPPORTED 1
#define CONFIG_SOC_PCNT_SUPPORTED 1
#define CONFIG_SOC_MCPWM_SUPPORTED 1
#define CONFIG_SOC_TWAI_SUPPORTED 1
#define CONFIG_SOC_ETM_SUPPORTED 1
#define CONFIG_SOC_PARLIO_SUPPORTED 1
#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1
#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1
#define CONFIG_SOC_WIFI_SUPPORTED 1
#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1
#define CONFIG_SOC_LP_CORE_SUPPORTED 1
#define CONFIG_SOC_ULP_SUPPORTED 1
#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define CONFIG_SOC_EFUSE_SUPPORTED 1
#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
#define CONFIG_SOC_RTC_MEM_SUPPORTED 1
#define CONFIG_SOC_I2S_SUPPORTED 1
#define CONFIG_SOC_RMT_SUPPORTED 1
#define CONFIG_SOC_SDM_SUPPORTED 1
#define CONFIG_SOC_GPSPI_SUPPORTED 1
#define CONFIG_SOC_LEDC_SUPPORTED 1
#define CONFIG_SOC_I2C_SUPPORTED 1
#define CONFIG_SOC_SYSTIMER_SUPPORTED 1
#define CONFIG_SOC_SUPPORT_COEXISTENCE 1
#define CONFIG_SOC_AES_SUPPORTED 1
#define CONFIG_SOC_MPI_SUPPORTED 1
#define CONFIG_SOC_SHA_SUPPORTED 1
#define CONFIG_SOC_RSA_SUPPORTED 1
#define CONFIG_SOC_HMAC_SUPPORTED 1
#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1
#define CONFIG_SOC_ECC_SUPPORTED 1
#define CONFIG_SOC_ECC_EXTENDED_MODES_SUPPORTED 1
#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1
#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1
#define CONFIG_SOC_IEEE802154_SUPPORTED 1
#define CONFIG_SOC_BOD_SUPPORTED 1
#define CONFIG_SOC_APM_SUPPORTED 1
#define CONFIG_SOC_PMU_SUPPORTED 1
#define CONFIG_SOC_PAU_SUPPORTED 1
#define CONFIG_SOC_LP_TIMER_SUPPORTED 1
#define CONFIG_SOC_LP_AON_SUPPORTED 1
#define CONFIG_SOC_LP_PERIPHERALS_SUPPORTED 1
#define CONFIG_SOC_LP_I2C_SUPPORTED 1
#define CONFIG_SOC_ULP_LP_UART_SUPPORTED 1
#define CONFIG_SOC_CLK_TREE_SUPPORTED 1
#define CONFIG_SOC_ASSIST_DEBUG_SUPPORTED 1
#define CONFIG_SOC_WDT_SUPPORTED 1
#define CONFIG_SOC_SDIO_SLAVE_SUPPORTED 1
#define CONFIG_SOC_SPI_FLASH_SUPPORTED 1
#define CONFIG_SOC_ECDSA_SUPPORTED 1
#define CONFIG_SOC_RNG_SUPPORTED 1
#define CONFIG_SOC_KEY_MANAGER_SUPPORTED 1
#define CONFIG_SOC_HUK_SUPPORTED 1
#define CONFIG_SOC_MODEM_CLOCK_SUPPORTED 1
#define CONFIG_SOC_LIGHT_SLEEP_SUPPORTED 1
#define CONFIG_SOC_DEEP_SLEEP_SUPPORTED 1
#define CONFIG_SOC_PM_SUPPORTED 1
#define CONFIG_SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED 1
#define CONFIG_SOC_SPIRAM_SUPPORTED 1
#define CONFIG_SOC_BT_SUPPORTED 1
#define CONFIG_SOC_PHY_SUPPORTED 1
#define CONFIG_SOC_BITSCRAMBLER_SUPPORTED 1
#define CONFIG_SOC_XTAL_SUPPORT_40M 1
#define CONFIG_SOC_XTAL_SUPPORT_48M 1
#define CONFIG_SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN 1
#define CONFIG_SOC_AES_SUPPORT_DMA 1
#define CONFIG_SOC_AES_GDMA 1
#define CONFIG_SOC_AES_SUPPORT_AES_128 1
#define CONFIG_SOC_AES_SUPPORT_AES_256 1
#define CONFIG_SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION 1
#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1
#define CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1
#define CONFIG_SOC_ADC_DMA_SUPPORTED 1
#define CONFIG_SOC_ADC_PERIPH_NUM 1
#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 6
#define CONFIG_SOC_ADC_ATTEN_NUM 4
#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 1
#define CONFIG_SOC_ADC_PATT_LEN_MAX 8
#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM 2
#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM 2
#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4
#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1
#define CONFIG_SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED 1
#define CONFIG_SOC_ADC_TEMPERATURE_SHARE_INTR 1
#define CONFIG_SOC_ADC_SHARED_POWER 1
#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1
#define CONFIG_SOC_SHARED_IDCACHE_SUPPORTED 1
#define CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED 1
#define CONFIG_SOC_CACHE_FREEZE_SUPPORTED 1
#define CONFIG_SOC_CPU_CORES_NUM 1
#define CONFIG_SOC_CPU_INTR_NUM 32
#define CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC 1
#define CONFIG_SOC_CPU_SUPPORT_WFE 1
#define CONFIG_SOC_INT_CLIC_SUPPORTED 1
#define CONFIG_SOC_INT_HW_NESTED_SUPPORTED 1
#define CONFIG_SOC_BRANCH_PREDICTOR_SUPPORTED 1
#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 4
#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 4
#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x100
#define CONFIG_SOC_CPU_HAS_PMA 1
#define CONFIG_SOC_CPU_IDRAM_SPLIT_USING_PMP 1
#define CONFIG_SOC_CPU_PMP_REGION_GRANULARITY 128
#define CONFIG_SOC_CPU_HAS_LOCKUP_RESET 1
#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 3072
#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16
#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100
#define CONFIG_SOC_DMA_CAN_ACCESS_FLASH 1
#define CONFIG_SOC_AHB_GDMA_VERSION 2
#define CONFIG_SOC_GDMA_NUM_GROUPS_MAX 1
#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define CONFIG_SOC_GDMA_SUPPORT_ETM 1
#define CONFIG_SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_AHB_GDMA_SUPPORT_PSRAM 1
#define CONFIG_SOC_ETM_GROUPS 1
#define CONFIG_SOC_ETM_CHANNELS_PER_GROUP 50
#define CONFIG_SOC_ETM_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_GPIO_PORT 1
#define CONFIG_SOC_GPIO_PIN_COUNT 29
#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define CONFIG_SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define CONFIG_SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
#define CONFIG_SOC_GPIO_SUPPORT_ETM 1
#define CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1
#define CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
#define CONFIG_SOC_LP_IO_CLOCK_IS_INDEPENDENT 1
#define CONFIG_SOC_GPIO_IN_RANGE_MAX 28
#define CONFIG_SOC_GPIO_OUT_RANGE_MAX 28
#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK 0
#define CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT 7
#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80
#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1
#define CONFIG_SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP 1
#define CONFIG_SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP 1
#define CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM 3
#define CONFIG_SOC_RTCIO_PIN_COUNT 7
#define CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define CONFIG_SOC_RTCIO_HOLD_SUPPORTED 1
#define CONFIG_SOC_RTCIO_WAKE_SUPPORTED 1
#define CONFIG_SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
#define CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM 8
#define CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM 8
#define CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE 1
#define CONFIG_SOC_ANA_CMPR_NUM 1
#define CONFIG_SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE 1
#define CONFIG_SOC_ANA_CMPR_SUPPORT_ETM 1
#define CONFIG_SOC_I2C_NUM 2
#define CONFIG_SOC_HP_I2C_NUM 1
#define CONFIG_SOC_I2C_FIFO_LEN 32
#define CONFIG_SOC_I2C_CMD_REG_NUM 8
#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1
#define CONFIG_SOC_I2C_SUPPORT_HW_FSM_RST 1
#define CONFIG_SOC_I2C_SUPPORT_XTAL 1
#define CONFIG_SOC_I2C_SUPPORT_RTC 1
#define CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR 1
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST 1
#define CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE 1
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS 1
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH 1
#define CONFIG_SOC_I2C_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_LP_I2C_NUM 1
#define CONFIG_SOC_LP_I2C_FIFO_LEN 16
#define CONFIG_SOC_I2S_NUM 1
#define CONFIG_SOC_I2S_HW_VERSION_2 1
#define CONFIG_SOC_I2S_SUPPORTS_ETM 1
#define CONFIG_SOC_I2S_SUPPORTS_XTAL 1
#define CONFIG_SOC_I2S_SUPPORTS_PLL_F160M 1
#define CONFIG_SOC_I2S_SUPPORTS_PLL_F240M 1
#define CONFIG_SOC_I2S_SUPPORTS_PCM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1
#define CONFIG_SOC_I2S_SUPPORTS_PCM2PDM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_RX 1
#define CONFIG_SOC_I2S_SUPPORTS_TX_SYNC_CNT 1
#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES 2
#define CONFIG_SOC_I2S_PDM_MAX_RX_LINES 1
#define CONFIG_SOC_I2S_SUPPORTS_TDM 1
#define CONFIG_SOC_I2S_TDM_FULL_DATA_WIDTH 1
#define CONFIG_SOC_I2S_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_LEDC_SUPPORT_PLL_DIV_CLOCK 1
#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1
#define CONFIG_SOC_LEDC_TIMER_NUM 4
#define CONFIG_SOC_LEDC_CHANNEL_NUM 6
#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH 20
#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1
#define CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED 1
#define CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX 16
#define CONFIG_SOC_LEDC_FADE_PARAMS_BIT_WIDTH 10
#define CONFIG_SOC_LEDC_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_MMU_PERIPH_NUM 1
#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 1
#define CONFIG_SOC_MMU_DI_VADDR_SHARED 1
#define CONFIG_SOC_PCNT_GROUPS 1
#define CONFIG_SOC_PCNT_UNITS_PER_GROUP 4
#define CONFIG_SOC_PCNT_CHANNELS_PER_UNIT 2
#define CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT 2
#define CONFIG_SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
#define CONFIG_SOC_PCNT_SUPPORT_CLEAR_SIGNAL 1
#define CONFIG_SOC_PCNT_SUPPORT_STEP_NOTIFY 1
#define CONFIG_SOC_PCNT_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_RMT_GROUPS 1
#define CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP 2
#define CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP 2
#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 4
#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48
#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1
#define CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION 1
#define CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1
#define CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO 1
#define CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1
#define CONFIG_SOC_RMT_SUPPORT_XTAL 1
#define CONFIG_SOC_RMT_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_MCPWM_GROUPS 1
#define CONFIG_SOC_MCPWM_TIMERS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR 2
#define CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR 2
#define CONFIG_SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR 2
#define CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR 2
#define CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP 1
#define CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3
#define CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1
#define CONFIG_SOC_MCPWM_SUPPORT_ETM 1
#define CONFIG_SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1
#define CONFIG_SOC_MCPWM_CAPTURE_CLK_FROM_GROUP 1
#define CONFIG_SOC_MCPWM_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_PARLIO_GROUPS 1
#define CONFIG_SOC_PARLIO_TX_UNITS_PER_GROUP 1
#define CONFIG_SOC_PARLIO_RX_UNITS_PER_GROUP 1
#define CONFIG_SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8
#define CONFIG_SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8
#define CONFIG_SOC_PARLIO_TX_CLK_SUPPORT_GATING 1
#define CONFIG_SOC_PARLIO_RX_CLK_SUPPORT_GATING 1
#define CONFIG_SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1
#define CONFIG_SOC_PARLIO_TRANS_BIT_ALIGN 1
#define CONFIG_SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1
#define CONFIG_SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA 1
#define CONFIG_SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_PARLIO_SUPPORT_SPI_LCD 1
#define CONFIG_SOC_PARLIO_SUPPORT_I80_LCD 1
#define CONFIG_SOC_MPI_MEM_BLOCKS_NUM 4
#define CONFIG_SOC_MPI_OPERATIONS_NUM 3
#define CONFIG_SOC_RSA_MAX_BIT_LEN 3072
#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968
#define CONFIG_SOC_SHA_SUPPORT_DMA 1
#define CONFIG_SOC_SHA_SUPPORT_RESUME 1
#define CONFIG_SOC_SHA_GDMA 1
#define CONFIG_SOC_SHA_SUPPORT_SHA1 1
#define CONFIG_SOC_SHA_SUPPORT_SHA224 1
#define CONFIG_SOC_SHA_SUPPORT_SHA256 1
#define CONFIG_SOC_SHA_SUPPORT_SHA384 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_224 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_256 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_T 1
#define CONFIG_SOC_ECC_CONSTANT_TIME_POINT_MUL 1
#define CONFIG_SOC_ECDSA_SUPPORT_EXPORT_PUBKEY 1
#define CONFIG_SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE 1
#define CONFIG_SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP 1
#define CONFIG_SOC_ECDSA_SUPPORT_CURVE_P384 1
#define CONFIG_SOC_SDM_GROUPS 1
#define CONFIG_SOC_SDM_CHANNELS_PER_GROUP 4
#define CONFIG_SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define CONFIG_SOC_SDM_CLK_SUPPORT_XTAL 1
#define CONFIG_SOC_SPI_PERIPH_NUM 2
#define CONFIG_SOC_SPI_MAX_CS_NUM 6
#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1
#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1
#define CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define CONFIG_SOC_SPI_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_XTAL 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_PLL_F160M 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_RC_FAST 1
#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1
#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16
#define CONFIG_SOC_SPIRAM_XIP_SUPPORTED 1
#define CONFIG_SOC_PSRAM_DMA_CAPABLE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_WRAP 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR 1
#define CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2
#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20
#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1
#define CONFIG_SOC_SYSTIMER_SUPPORT_RC_FAST 1
#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1
#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1
#define CONFIG_SOC_SYSTIMER_SUPPORT_ETM 1
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO 32
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI 16
#define CONFIG_SOC_TIMER_GROUPS 2
#define CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP 1
#define CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 54
#define CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL 1
#define CONFIG_SOC_TIMER_GROUP_SUPPORT_RC_FAST 1
#define CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS 2
#define CONFIG_SOC_TIMER_SUPPORT_ETM 1
#define CONFIG_SOC_TIMER_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_MWDT_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_TWAI_CONTROLLER_NUM 2
#define CONFIG_SOC_TWAI_MASK_FILTER_NUM 3
#define CONFIG_SOC_TWAI_RANGE_FILTER_NUM 1
#define CONFIG_SOC_TWAI_BRP_MIN 1
#define CONFIG_SOC_TWAI_BRP_MAX 255
#define CONFIG_SOC_TWAI_CLK_SUPPORT_XTAL 1
#define CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS 1
#define CONFIG_SOC_TWAI_SUPPORT_FD 1
#define CONFIG_SOC_TWAI_SUPPORT_TIMESTAMP 1
#define CONFIG_SOC_EFUSE_DIS_PAD_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1
#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_ICACHE 1
#define CONFIG_SOC_EFUSE_ECDSA_KEY 1
#define CONFIG_SOC_EFUSE_ECDSA_KEY_P192 1
#define CONFIG_SOC_EFUSE_ECDSA_KEY_P384 1
#define CONFIG_SOC_HUK_MEM_NEEDS_RECHARGE 1
#define CONFIG_SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1
#define CONFIG_SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1
#define CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY 1
#define CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 1
#define CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 1
#define CONFIG_SOC_KEY_MANAGER_HMAC_KEY_DEPLOY 1
#define CONFIG_SOC_KEY_MANAGER_DS_KEY_DEPLOY 1
#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1
#define CONFIG_SOC_SECURE_BOOT_V2_ECC 1
#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX 64
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND 1
#define CONFIG_SOC_PSRAM_ENCRYPTION_XTS_AES_128 1
#define CONFIG_SOC_RECOVERY_BOOTLOADER_SUPPORTED 1
#define CONFIG_SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED 1
#define CONFIG_SOC_APM_CTRL_FILTER_SUPPORTED 1
#define CONFIG_SOC_APM_LP_APM0_SUPPORTED 1
#define CONFIG_SOC_APM_CPU_APM_SUPPORTED 1
#define CONFIG_SOC_APM_SUPPORT_LP_TEE_CTRL 1
#define CONFIG_SOC_APM_SUPPORT_CTRL_CFG_LOCK 1
#define CONFIG_SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL 1
#define CONFIG_SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
#define CONFIG_SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE 1
#define CONFIG_SOC_RNG_RTC_TIMER_ENTROPY_SOURCE 1
#define CONFIG_SOC_UART_NUM 3
#define CONFIG_SOC_UART_HP_NUM 2
#define CONFIG_SOC_UART_LP_NUM 1
#define CONFIG_SOC_UART_FIFO_LEN 128
#define CONFIG_SOC_LP_UART_FIFO_LEN 16
#define CONFIG_SOC_UART_BITRATE_MAX 5000000
#define CONFIG_SOC_UART_SUPPORT_PLL_F80M_CLK 1
#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1
#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1
#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1
#define CONFIG_SOC_UART_HAS_LP_UART 1
#define CONFIG_SOC_UART_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND 1
#define CONFIG_SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE 1
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE 1
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE 1
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE 1
#define CONFIG_SOC_UHCI_NUM 1
#define CONFIG_SOC_COEX_HW_PTI 1
#define CONFIG_SOC_EXTERNAL_COEX_ADVANCE 1
#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12
#define CONFIG_SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH 1
#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_BEACON_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN 1
#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1
#define CONFIG_SOC_PM_SUPPORT_MODEM_PD 1
#define CONFIG_SOC_PM_SUPPORT_XTAL32K_PD 1
#define CONFIG_SOC_PM_SUPPORT_RC32K_PD 1
#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1
#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1
#define CONFIG_SOC_PM_SUPPORT_TOP_PD 1
#define CONFIG_SOC_PM_SUPPORT_HP_AON_PD 1
#define CONFIG_SOC_PM_SUPPORT_MAC_BB_PD 1
#define CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD 1
#define CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE 1
#define CONFIG_SOC_PM_SUPPORT_PMU_CLK_ICG 1
#define CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY 1
#define CONFIG_SOC_PM_CPU_RETENTION_BY_SW 1
#define CONFIG_SOC_PM_MODEM_RETENTION_BY_REGDMA 1
#define CONFIG_SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN 1
#define CONFIG_SOC_PM_TOP_PD_NOT_ALLOWED 1
#define CONFIG_SOC_PM_PAU_LINK_NUM 5
#define CONFIG_SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE 1
#define CONFIG_SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC 4
#define CONFIG_SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED 1
#define CONFIG_SOC_PM_RETENTION_MODULE_NUM 32
#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1
#define CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT 1
#define CONFIG_SOC_RNG_CLOCK_IS_INDEPENDENT 1
#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1
#define CONFIG_SOC_CLK_OSC_SLOW_SUPPORTED 1
#define CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL 1
#define CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 1
#define CONFIG_SOC_RCC_IS_INDEPENDENT 1
#define CONFIG_SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_INTR_SUPPORT 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN 1
#define CONFIG_SOC_WIFI_HW_TSF 1
#define CONFIG_SOC_WIFI_FTM_SUPPORT 1
#define CONFIG_SOC_WIFI_GCMP_SUPPORT 1
#define CONFIG_SOC_WIFI_WAPI_SUPPORT 1
#define CONFIG_SOC_WIFI_CSI_SUPPORT 1
#define CONFIG_SOC_WIFI_MESH_SUPPORT 1
#define CONFIG_SOC_WIFI_HE_SUPPORT 1
#define CONFIG_SOC_WIFI_SUPPORT_5G 1
#define CONFIG_SOC_WIFI_MAC_VERSION_NUM 3
#define CONFIG_SOC_WIFI_NAN_SUPPORT 1
#define CONFIG_SOC_BLE_SUPPORTED 1
#define CONFIG_SOC_ESP_NIMBLE_CONTROLLER 1
#define CONFIG_SOC_BLE_50_SUPPORTED 1
#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1
#define CONFIG_SOC_BLE_POWER_CONTROL_SUPPORTED 1
#define CONFIG_SOC_BLE_MULTI_CONN_OPTIMIZATION 1
#define CONFIG_SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED 1
#define CONFIG_SOC_BLE_CTE_SUPPORTED 1
#define CONFIG_SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT 1
#define CONFIG_SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR 1
#define CONFIG_SOC_LP_CORE_SUPPORT_ETM 1
#define CONFIG_SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS 1
#define CONFIG_IDF_CMAKE 1
#define CONFIG_IDF_ENV_BRINGUP 1
#define CONFIG_IDF_TOOLCHAIN "gcc"
#define CONFIG_IDF_TOOLCHAIN_GCC 1
#define CONFIG_IDF_TARGET_ARCH_RISCV 1
#define CONFIG_IDF_TARGET_ARCH "riscv"
#define CONFIG_IDF_TARGET "esp32c5"
#define CONFIG_IDF_INIT_VERSION "5.5.1"
#define CONFIG_IDF_TARGET_ESP32C5 1
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0017
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
#define CONFIG_APP_BUILD_BOOTLOADER 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_BOOTLOADER_COMPILE_TIME_DATE 1
#define CONFIG_BOOTLOADER_PROJECT_VER 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x2000
#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
#define CONFIG_BOOTLOADER_LOG_VERSION_1 1
#define CONFIG_BOOTLOADER_LOG_VERSION 1
#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1
#define CONFIG_BOOTLOADER_LOG_LEVEL 3
#define CONFIG_BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS 1
#define CONFIG_BOOTLOADER_LOG_MODE_TEXT_EN 1
#define CONFIG_BOOTLOADER_LOG_MODE_TEXT 1
#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1
#define CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE 1
#define CONFIG_BOOTLOADER_WDT_ENABLE 1
#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0
#define CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED 1
#define CONFIG_SECURE_BOOT_V2_ECC_SUPPORTED 1
#define CONFIG_SECURE_BOOT_V2_PREFERRED 1
#define CONFIG_SECURE_ROM_DL_MODE_ENABLED 1
#define CONFIG_APP_COMPILE_TIME_DATE 1
#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 9
#define CONFIG_ESP_ROM_HAS_CRC_LE 1
#define CONFIG_ESP_ROM_HAS_CRC_BE 1
#define CONFIG_ESP_ROM_HAS_JPEG_DECODE 1
#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1
#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 3
#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1
#define CONFIG_ESP_ROM_GET_CLK_FREQ 1
#define CONFIG_ESP_ROM_HAS_RVFPLIB 1
#define CONFIG_ESP_ROM_HAS_HAL_WDT 1
#define CONFIG_ESP_ROM_HAS_HAL_SYSTIMER 1
#define CONFIG_ESP_ROM_SYSTIMER_INIT_PATCH 1
#define CONFIG_ESP_ROM_HAS_HEAP_TLSF 1
#define CONFIG_ESP_ROM_TLSF_CHECK_PATCH 1
#define CONFIG_ESP_ROM_MULTI_HEAP_WALK_PATCH 1
#define CONFIG_ESP_ROM_HAS_LAYOUT_TABLE 1
#define CONFIG_ESP_ROM_HAS_SPI_FLASH 1
#define CONFIG_ESP_ROM_HAS_SPI_FLASH_MMAP 1
#define CONFIG_ESP_ROM_WITHOUT_REGI2C 1
#define CONFIG_ESP_ROM_HAS_NEWLIB 1
#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT 1
#define CONFIG_ESP_ROM_WDT_INIT_PATCH 1
#define CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE 1
#define CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT 1
#define CONFIG_ESP_ROM_HAS_VERSION 1
#define CONFIG_ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB 1
#define CONFIG_ESP_ROM_USB_OTG_NUM -1
#define CONFIG_ESP_ROM_HAS_OUTPUT_PUTC_FUNC 1
#define CONFIG_ESP_ROM_CLIC_INT_THRESH_PATCH 1
#define CONFIG_ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY 1
#define CONFIG_ESP_ROM_DELAY_US_PATCH 1
#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1
#define CONFIG_ESPTOOLPY_NO_STUB 1
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1
#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB"
#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
#define CONFIG_ESPTOOLPY_AFTER_RESET 1
#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200
#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
#define CONFIG_PARTITION_TABLE_MD5 1
#define CONFIG_COMPILER_OPTIMIZATION_DEBUG 1
#define CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE 1
#define CONFIG_COMPILER_ASSERT_NDEBUG_EVALUATE 1
#define CONFIG_COMPILER_FLOAT_LIB_FROM_RVFPLIB 1
#define CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL 2
#define CONFIG_COMPILER_HIDE_PATHS_MACROS 1
#define CONFIG_COMPILER_STACK_CHECK_MODE_NONE 1
#define CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS 1
#define CONFIG_COMPILER_RT_LIB_GCCLIB 1
#define CONFIG_COMPILER_RT_LIB_NAME "gcc"
#define CONFIG_COMPILER_ORPHAN_SECTIONS_WARNING 1
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1
#define CONFIG_ESP32C5_REV_MIN_100 1
#define CONFIG_ESP32C5_REV_MIN_FULL 100
#define CONFIG_ESP_REV_MIN_FULL 100
#define CONFIG_ESP32C5_REV_MAX_FULL 199
#define CONFIG_ESP_REV_MAX_FULL 199
#define CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL 0
#define CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL 99
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_IEEE802154 1
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR 1
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES 4
#define CONFIG_ESP32C5_UNIVERSAL_MAC_ADDRESSES_FOUR 1
#define CONFIG_ESP32C5_UNIVERSAL_MAC_ADDRESSES 4
#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 1
#define CONFIG_RTC_CLK_SRC_INT_RC 1
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
#define CONFIG_RTC_FAST_CLK_SRC_RC_FAST 1
#define CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM 1
#define CONFIG_ESP_REGI2C_CTRL_FUNC_IN_IRAM 1
#define CONFIG_GDMA_CTRL_FUNC_IN_IRAM 1
#define CONFIG_GDMA_ISR_HANDLER_IN_IRAM 1
#define CONFIG_GDMA_OBJ_DRAM_SAFE 1
#define CONFIG_XTAL_FREQ_AUTO 1
#define CONFIG_XTAL_FREQ 0
#define CONFIG_ESP_BROWNOUT_DET 1
#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1
#define CONFIG_ESP_BROWNOUT_DET_LVL 7
#define CONFIG_ESP_BROWNOUT_USE_INTR 1
#define CONFIG_ESP_CLK_RC32K_NOT_TO_USE 1
#define CONFIG_ESP_INTR_IN_IRAM 1
#define CONFIG_ESP_ROM_PRINT_IN_IRAM 1
#define CONFIG_ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP 1
#define CONFIG_ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW 1
#define CONFIG_ESP_CRYPTO_DPA_PROTECTION_LEVEL 1
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 1
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
#define CONFIG_CACHE_L1_CACHE_SIZE 0x8000
#define CONFIG_CACHE_L1_CACHE_LINE_SIZE 32
#define CONFIG_ESP_SYSTEM_IN_IRAM 1
#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1
#define CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS 0
#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1
#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1
#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1
#define CONFIG_ESP_SYSTEM_NO_BACKTRACE 1
#define CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT 1
#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2304
#define CONFIG_ESP_MAIN_TASK_STACK_SIZE 3584
#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1
#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0
#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048
#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1
#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED 1
#define CONFIG_ESP_CONSOLE_UART 1
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM 0
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
#define CONFIG_ESP_INT_WDT 1
#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
#define CONFIG_ESP_TASK_WDT_EN 1
#define CONFIG_ESP_TASK_WDT_INIT 1
#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
#define CONFIG_ESP_SYSTEM_HW_STACK_GUARD 1
#define CONFIG_ESP_SYSTEM_HW_PC_RECORD 1
#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024
#define CONFIG_FREERTOS_UNICORE 1
#define CONFIG_FREERTOS_HZ 100
#define CONFIG_FREERTOS_OPTIMIZED_SCHEDULER 1
#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536
#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
#define CONFIG_FREERTOS_USE_TIMERS 1
#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_NAME "Tmr Svc"
#define CONFIG_FREERTOS_TIMER_TASK_NO_AFFINITY 1
#define CONFIG_FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY 0x7FFFFFFF
#define CONFIG_FREERTOS_TIMER_TASK_PRIORITY 1
#define CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH 2048
#define CONFIG_FREERTOS_TIMER_QUEUE_LENGTH 10
#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0
#define CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES 1
#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1
#define CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS 1
#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1
#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1
#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1
#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1
#define CONFIG_FREERTOS_PORT 1
#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF
#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1
#define CONFIG_FREERTOS_DEBUG_OCDAWARE 1
#define CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT 1
#define CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH 1
#define CONFIG_FREERTOS_NUMBER_OF_CORES 1
#define CONFIG_FREERTOS_IN_IRAM 1
#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1
#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2
#define CONFIG_HAL_SYSTIMER_USE_ROM_IMPL 1
#define CONFIG_HAL_WDT_USE_ROM_IMPL 1
#define CONFIG_LOG_VERSION_1 1
#define CONFIG_LOG_VERSION 1
#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1
#define CONFIG_LOG_MAXIMUM_LEVEL 3
#define CONFIG_LOG_DYNAMIC_LEVEL_CONTROL 1
#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST 1
#define CONFIG_LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP 1
#define CONFIG_LOG_TAG_LEVEL_IMPL_CACHE_SIZE 31
#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
#define CONFIG_LOG_MODE_TEXT_EN 1
#define CONFIG_LOG_MODE_TEXT 1
#define CONFIG_LOG_IN_IRAM 1
#define CONFIG_LIBC_NEWLIB 1
#define CONFIG_LIBC_MISC_IN_IRAM 1
#define CONFIG_LIBC_LOCKS_PLACE_IN_IRAM 1
#define CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT 1
#define CONFIG_MMU_PAGE_SIZE_64KB 1
#define CONFIG_MMU_PAGE_MODE "64KB"
#define CONFIG_MMU_PAGE_SIZE 0x10000
#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1
#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1
#define CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US 50
#define CONFIG_SPI_FLASH_SUSPEND_TRS_VAL_US 50
#define CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM 1
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20
#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1
#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192
#define CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED 1
#define CONFIG_SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED 1
#define CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED 1
#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1
#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1
/* List of deprecated options */
#define CONFIG_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
#define CONFIG_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR CONFIG_ESP_BROWNOUT_USE_INTR
#define CONFIG_ESP_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO
#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT
#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO CONFIG_BOOTLOADER_LOG_LEVEL_INFO
#define CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
#define CONFIG_MONITOR_BAUD CONFIG_ESPTOOLPY_MONITOR_BAUD
#define CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT
#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE
#define CONFIG_OPTIMIZATION_ASSERTION_LEVEL CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL
#define CONFIG_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_PERIPH_CTRL_FUNC_IN_IRAM CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM
#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
#define CONFIG_STACK_CHECK_NONE CONFIG_COMPILER_STACK_CHECK_MODE_NONE
#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH
#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY
#define CONFIG_TIMER_TASK_STACK_DEPTH CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH
v2x_fw/build/bootloader/config/sdkconfig.json
+880
View File
@@ -0,0 +1,880 @@
{
"APP_BUILD_BOOTLOADER": true,
"APP_BUILD_GENERATE_BINARIES": true,
"APP_BUILD_TYPE_APP_2NDBOOT": true,
"APP_BUILD_TYPE_RAM": false,
"APP_BUILD_USE_FLASH_SECTIONS": true,
"APP_COMPILE_TIME_DATE": true,
"APP_EXCLUDE_PROJECT_NAME_VAR": false,
"APP_EXCLUDE_PROJECT_VER_VAR": false,
"APP_NO_BLOBS": false,
"APP_PROJECT_VER_FROM_CONFIG": false,
"APP_REPRODUCIBLE_BUILD": false,
"APP_RETRIEVE_LEN_ELF_SHA": 9,
"BOOTLOADER_APP_ROLLBACK_ENABLE": false,
"BOOTLOADER_APP_TEST": false,
"BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG": false,
"BOOTLOADER_COMPILER_OPTIMIZATION_PERF": false,
"BOOTLOADER_COMPILER_OPTIMIZATION_SIZE": true,
"BOOTLOADER_COMPILE_TIME_DATE": true,
"BOOTLOADER_CUSTOM_RESERVE_RTC": false,
"BOOTLOADER_FACTORY_RESET": false,
"BOOTLOADER_FLASH_DC_AWARE": false,
"BOOTLOADER_FLASH_XMC_SUPPORT": true,
"BOOTLOADER_LOG_COLORS": false,
"BOOTLOADER_LOG_LEVEL": 3,
"BOOTLOADER_LOG_LEVEL_DEBUG": false,
"BOOTLOADER_LOG_LEVEL_ERROR": false,
"BOOTLOADER_LOG_LEVEL_INFO": true,
"BOOTLOADER_LOG_LEVEL_NONE": false,
"BOOTLOADER_LOG_LEVEL_VERBOSE": false,
"BOOTLOADER_LOG_LEVEL_WARN": false,
"BOOTLOADER_LOG_MODE_TEXT": true,
"BOOTLOADER_LOG_MODE_TEXT_EN": true,
"BOOTLOADER_LOG_TIMESTAMP_SOURCE_CPU_TICKS": true,
"BOOTLOADER_LOG_VERSION": 1,
"BOOTLOADER_LOG_VERSION_1": true,
"BOOTLOADER_OFFSET_IN_FLASH": 8192,
"BOOTLOADER_PROJECT_VER": 1,
"BOOTLOADER_RECOVERY_ENABLE": false,
"BOOTLOADER_REGION_PROTECTION_ENABLE": true,
"BOOTLOADER_RESERVE_RTC_SIZE": 0,
"BOOTLOADER_SKIP_VALIDATE_ALWAYS": false,
"BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP": false,
"BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON": false,
"BOOTLOADER_WDT_DISABLE_IN_USER_CODE": false,
"BOOTLOADER_WDT_ENABLE": true,
"BOOTLOADER_WDT_TIME_MS": 9000,
"BOOT_ROM_LOG_ALWAYS_OFF": false,
"BOOT_ROM_LOG_ALWAYS_ON": true,
"BOOT_ROM_LOG_ON_GPIO_HIGH": false,
"BOOT_ROM_LOG_ON_GPIO_LOW": false,
"CACHE_L1_CACHE_LINE_SIZE": 32,
"CACHE_L1_CACHE_SIZE": 32768,
"COMPILER_ASSERT_NDEBUG_EVALUATE": true,
"COMPILER_CXX_EXCEPTIONS": false,
"COMPILER_CXX_RTTI": false,
"COMPILER_DISABLE_DEFAULT_ERRORS": true,
"COMPILER_DISABLE_GCC12_WARNINGS": false,
"COMPILER_DISABLE_GCC13_WARNINGS": false,
"COMPILER_DISABLE_GCC14_WARNINGS": false,
"COMPILER_DUMP_RTL_FILES": false,
"COMPILER_FLOAT_LIB_FROM_GCCLIB": false,
"COMPILER_FLOAT_LIB_FROM_RVFPLIB": true,
"COMPILER_HIDE_PATHS_MACROS": true,
"COMPILER_NO_MERGE_CONSTANTS": false,
"COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE": false,
"COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE": true,
"COMPILER_OPTIMIZATION_ASSERTIONS_SILENT": false,
"COMPILER_OPTIMIZATION_ASSERTION_LEVEL": 2,
"COMPILER_OPTIMIZATION_CHECKS_SILENT": false,
"COMPILER_OPTIMIZATION_DEBUG": true,
"COMPILER_OPTIMIZATION_NONE": false,
"COMPILER_OPTIMIZATION_PERF": false,
"COMPILER_OPTIMIZATION_SIZE": false,
"COMPILER_ORPHAN_SECTIONS_PLACE": false,
"COMPILER_ORPHAN_SECTIONS_WARNING": true,
"COMPILER_RT_LIB_GCCLIB": true,
"COMPILER_RT_LIB_NAME": "gcc",
"COMPILER_SAVE_RESTORE_LIBCALLS": false,
"COMPILER_STACK_CHECK_MODE_ALL": false,
"COMPILER_STACK_CHECK_MODE_NONE": true,
"COMPILER_STACK_CHECK_MODE_NORM": false,
"COMPILER_STACK_CHECK_MODE_STRONG": false,
"COMPILER_STATIC_ANALYZER": false,
"COMPILER_WARN_WRITE_STRINGS": false,
"EFUSE_CUSTOM_TABLE": false,
"EFUSE_MAX_BLK_LEN": 256,
"EFUSE_VIRTUAL": false,
"ESP32C5_REV_MAX_FULL": 199,
"ESP32C5_REV_MIN_100": true,
"ESP32C5_REV_MIN_FULL": 100,
"ESP32C5_UNIVERSAL_MAC_ADDRESSES": 4,
"ESP32C5_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
"ESP32C5_UNIVERSAL_MAC_ADDRESSES_TWO": false,
"ESPTOOLPY_AFTER": "hard_reset",
"ESPTOOLPY_AFTER_NORESET": false,
"ESPTOOLPY_AFTER_RESET": true,
"ESPTOOLPY_BEFORE": "default_reset",
"ESPTOOLPY_BEFORE_NORESET": false,
"ESPTOOLPY_BEFORE_RESET": true,
"ESPTOOLPY_FLASHFREQ": "80m",
"ESPTOOLPY_FLASHFREQ_20M": false,
"ESPTOOLPY_FLASHFREQ_40M": false,
"ESPTOOLPY_FLASHFREQ_80M": true,
"ESPTOOLPY_FLASHMODE": "dio",
"ESPTOOLPY_FLASHMODE_DIO": true,
"ESPTOOLPY_FLASHMODE_DOUT": false,
"ESPTOOLPY_FLASHMODE_QIO": false,
"ESPTOOLPY_FLASHMODE_QOUT": false,
"ESPTOOLPY_FLASHSIZE": "2MB",
"ESPTOOLPY_FLASHSIZE_128MB": false,
"ESPTOOLPY_FLASHSIZE_16MB": false,
"ESPTOOLPY_FLASHSIZE_1MB": false,
"ESPTOOLPY_FLASHSIZE_2MB": true,
"ESPTOOLPY_FLASHSIZE_32MB": false,
"ESPTOOLPY_FLASHSIZE_4MB": false,
"ESPTOOLPY_FLASHSIZE_64MB": false,
"ESPTOOLPY_FLASHSIZE_8MB": false,
"ESPTOOLPY_FLASH_SAMPLE_MODE_STR": true,
"ESPTOOLPY_HEADER_FLASHSIZE_UPDATE": false,
"ESPTOOLPY_MONITOR_BAUD": 115200,
"ESPTOOLPY_NO_STUB": true,
"ESP_BROWNOUT_DET": true,
"ESP_BROWNOUT_DET_LVL": 7,
"ESP_BROWNOUT_DET_LVL_SEL_2": false,
"ESP_BROWNOUT_DET_LVL_SEL_3": false,
"ESP_BROWNOUT_DET_LVL_SEL_4": false,
"ESP_BROWNOUT_DET_LVL_SEL_5": false,
"ESP_BROWNOUT_DET_LVL_SEL_6": false,
"ESP_BROWNOUT_DET_LVL_SEL_7": true,
"ESP_BROWNOUT_USE_INTR": true,
"ESP_CLK_RC32K_NOT_TO_USE": true,
"ESP_CONSOLE_NONE": false,
"ESP_CONSOLE_ROM_SERIAL_PORT_NUM": 0,
"ESP_CONSOLE_SECONDARY_NONE": false,
"ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG": true,
"ESP_CONSOLE_UART": true,
"ESP_CONSOLE_UART_BAUDRATE": 115200,
"ESP_CONSOLE_UART_CUSTOM": false,
"ESP_CONSOLE_UART_DEFAULT": true,
"ESP_CONSOLE_UART_NUM": 0,
"ESP_CONSOLE_USB_SERIAL_JTAG": false,
"ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED": true,
"ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP": true,
"ESP_CRYPTO_DPA_PROTECTION_LEVEL": 1,
"ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH": false,
"ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW": true,
"ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM": false,
"ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL": false,
"ESP_DEBUG_OCDAWARE": true,
"ESP_DEBUG_STUBS_ENABLE": false,
"ESP_DEFAULT_CPU_FREQ_MHZ": 240,
"ESP_DEFAULT_CPU_FREQ_MHZ_160": false,
"ESP_DEFAULT_CPU_FREQ_MHZ_240": true,
"ESP_DEFAULT_CPU_FREQ_MHZ_80": false,
"ESP_EFUSE_BLOCK_REV_MAX_FULL": 99,
"ESP_EFUSE_BLOCK_REV_MIN_FULL": 0,
"ESP_ERR_TO_NAME_LOOKUP": true,
"ESP_INTR_IN_IRAM": true,
"ESP_INT_WDT": true,
"ESP_INT_WDT_TIMEOUT_MS": 300,
"ESP_IPC_TASK_STACK_SIZE": 1024,
"ESP_MAC_ADDR_UNIVERSE_BT": true,
"ESP_MAC_ADDR_UNIVERSE_ETH": true,
"ESP_MAC_ADDR_UNIVERSE_IEEE802154": true,
"ESP_MAC_ADDR_UNIVERSE_WIFI_AP": true,
"ESP_MAC_ADDR_UNIVERSE_WIFI_STA": true,
"ESP_MAC_UNIVERSAL_MAC_ADDRESSES": 4,
"ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
"ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC": false,
"ESP_MAIN_TASK_AFFINITY": 0,
"ESP_MAIN_TASK_AFFINITY_CPU0": true,
"ESP_MAIN_TASK_AFFINITY_NO_AFFINITY": false,
"ESP_MAIN_TASK_STACK_SIZE": 3584,
"ESP_MINIMAL_SHARED_STACK_SIZE": 2048,
"ESP_PANIC_HANDLER_IRAM": false,
"ESP_PERIPH_CTRL_FUNC_IN_IRAM": true,
"ESP_REGI2C_CTRL_FUNC_IN_IRAM": true,
"ESP_REV_MAX_FULL": 199,
"ESP_REV_MIN_FULL": 100,
"ESP_ROM_CLIC_INT_THRESH_PATCH": true,
"ESP_ROM_DELAY_US_PATCH": true,
"ESP_ROM_GET_CLK_FREQ": true,
"ESP_ROM_HAS_CRC_BE": true,
"ESP_ROM_HAS_CRC_LE": true,
"ESP_ROM_HAS_HAL_SYSTIMER": true,
"ESP_ROM_HAS_HAL_WDT": true,
"ESP_ROM_HAS_HEAP_TLSF": true,
"ESP_ROM_HAS_JPEG_DECODE": true,
"ESP_ROM_HAS_LAYOUT_TABLE": true,
"ESP_ROM_HAS_NEWLIB": true,
"ESP_ROM_HAS_NEWLIB_NANO_FORMAT": true,
"ESP_ROM_HAS_OUTPUT_PUTC_FUNC": true,
"ESP_ROM_HAS_RETARGETABLE_LOCKING": true,
"ESP_ROM_HAS_RVFPLIB": true,
"ESP_ROM_HAS_SPI_FLASH": true,
"ESP_ROM_HAS_SPI_FLASH_MMAP": true,
"ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY": true,
"ESP_ROM_HAS_VERSION": true,
"ESP_ROM_MULTI_HEAP_WALK_PATCH": true,
"ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE": true,
"ESP_ROM_PRINT_IN_IRAM": true,
"ESP_ROM_RAM_APP_NEEDS_MMU_INIT": true,
"ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB": true,
"ESP_ROM_SYSTIMER_INIT_PATCH": true,
"ESP_ROM_TLSF_CHECK_PATCH": true,
"ESP_ROM_UART_CLK_IS_XTAL": true,
"ESP_ROM_USB_OTG_NUM": -1,
"ESP_ROM_USB_SERIAL_DEVICE_NUM": 3,
"ESP_ROM_WDT_INIT_PATCH": true,
"ESP_ROM_WITHOUT_REGI2C": true,
"ESP_SLEEP_CACHE_SAFE_ASSERTION": false,
"ESP_SLEEP_DEBUG": false,
"ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND": true,
"ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS": true,
"ESP_SLEEP_GPIO_RESET_WORKAROUND": true,
"ESP_SLEEP_MSPI_NEED_ALL_IO_PU": false,
"ESP_SLEEP_POWER_DOWN_FLASH": false,
"ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY": 0,
"ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP": true,
"ESP_SYSTEM_CHECK_INT_LEVEL_4": true,
"ESP_SYSTEM_EVENT_QUEUE_SIZE": 32,
"ESP_SYSTEM_EVENT_TASK_STACK_SIZE": 2304,
"ESP_SYSTEM_HW_PC_RECORD": true,
"ESP_SYSTEM_HW_STACK_GUARD": true,
"ESP_SYSTEM_IN_IRAM": true,
"ESP_SYSTEM_NO_BACKTRACE": true,
"ESP_SYSTEM_PANIC_PRINT_HALT": false,
"ESP_SYSTEM_PANIC_PRINT_REBOOT": true,
"ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS": 0,
"ESP_SYSTEM_PANIC_SILENT_REBOOT": false,
"ESP_SYSTEM_PMP_IDRAM_SPLIT": true,
"ESP_SYSTEM_PMP_LP_CORE_RESERVE_MEM_EXECUTABLE": false,
"ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK": true,
"ESP_SYSTEM_SINGLE_CORE_MODE": true,
"ESP_SYSTEM_USE_EH_FRAME": false,
"ESP_SYSTEM_USE_FRAME_POINTER": false,
"ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0": true,
"ESP_TASK_WDT_EN": true,
"ESP_TASK_WDT_INIT": true,
"ESP_TASK_WDT_PANIC": false,
"ESP_TASK_WDT_TIMEOUT_S": 5,
"ETM_ENABLE_DEBUG_LOG": false,
"FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER": true,
"FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE": false,
"FREERTOS_CHECK_STACKOVERFLOW_CANARY": true,
"FREERTOS_CHECK_STACKOVERFLOW_NONE": false,
"FREERTOS_CHECK_STACKOVERFLOW_PTRVAL": false,
"FREERTOS_CORETIMER_SYSTIMER_LVL1": true,
"FREERTOS_CORETIMER_SYSTIMER_LVL3": false,
"FREERTOS_DEBUG_OCDAWARE": true,
"FREERTOS_ENABLE_BACKWARD_COMPATIBILITY": false,
"FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP": false,
"FREERTOS_ENABLE_TASK_SNAPSHOT": true,
"FREERTOS_GENERATE_RUN_TIME_STATS": false,
"FREERTOS_HZ": 100,
"FREERTOS_IDLE_TASK_STACKSIZE": 1536,
"FREERTOS_INTERRUPT_BACKTRACE": true,
"FREERTOS_IN_IRAM": true,
"FREERTOS_ISR_STACKSIZE": 1536,
"FREERTOS_MAX_TASK_NAME_LEN": 16,
"FREERTOS_NO_AFFINITY": 2147483647,
"FREERTOS_NUMBER_OF_CORES": 1,
"FREERTOS_OPTIMIZED_SCHEDULER": true,
"FREERTOS_PLACE_FUNCTIONS_INTO_FLASH": false,
"FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH": true,
"FREERTOS_PORT": true,
"FREERTOS_QUEUE_REGISTRY_SIZE": 0,
"FREERTOS_SMP": false,
"FREERTOS_SUPPORT_STATIC_ALLOCATION": true,
"FREERTOS_SYSTICK_USES_SYSTIMER": true,
"FREERTOS_TASK_FUNCTION_WRAPPER": true,
"FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES": 1,
"FREERTOS_TASK_PRE_DELETION_HOOK": false,
"FREERTOS_THREAD_LOCAL_STORAGE_POINTERS": 1,
"FREERTOS_TICK_SUPPORT_SYSTIMER": true,
"FREERTOS_TIMER_QUEUE_LENGTH": 10,
"FREERTOS_TIMER_SERVICE_TASK_CORE_AFFINITY": 2147483647,
"FREERTOS_TIMER_SERVICE_TASK_NAME": "Tmr Svc",
"FREERTOS_TIMER_TASK_AFFINITY_CPU0": false,
"FREERTOS_TIMER_TASK_NO_AFFINITY": true,
"FREERTOS_TIMER_TASK_PRIORITY": 1,
"FREERTOS_TIMER_TASK_STACK_DEPTH": 2048,
"FREERTOS_TLSP_DELETION_CALLBACKS": true,
"FREERTOS_UNICORE": true,
"FREERTOS_USE_APPLICATION_TASK_TAG": false,
"FREERTOS_USE_IDLE_HOOK": false,
"FREERTOS_USE_LIST_DATA_INTEGRITY_CHECK_BYTES": false,
"FREERTOS_USE_TICK_HOOK": false,
"FREERTOS_USE_TIMERS": true,
"FREERTOS_USE_TRACE_FACILITY": false,
"FREERTOS_WATCHPOINT_END_OF_STACK": false,
"GDMA_CTRL_FUNC_IN_IRAM": true,
"GDMA_ENABLE_DEBUG_LOG": false,
"GDMA_ISR_HANDLER_IN_IRAM": true,
"GDMA_ISR_IRAM_SAFE": false,
"GDMA_OBJ_DRAM_SAFE": true,
"HAL_ASSERTION_DISABLE": false,
"HAL_ASSERTION_ENABLE": false,
"HAL_ASSERTION_EQUALS_SYSTEM": true,
"HAL_ASSERTION_SILENT": false,
"HAL_DEFAULT_ASSERTION_LEVEL": 2,
"HAL_SYSTIMER_USE_ROM_IMPL": true,
"HAL_WDT_USE_ROM_IMPL": true,
"IDF_CMAKE": true,
"IDF_ENV_BRINGUP": true,
"IDF_EXPERIMENTAL_FEATURES": false,
"IDF_FIRMWARE_CHIP_ID": 23,
"IDF_INIT_VERSION": "5.5.1",
"IDF_TARGET": "esp32c5",
"IDF_TARGET_ARCH": "riscv",
"IDF_TARGET_ARCH_RISCV": true,
"IDF_TARGET_ESP32C5": true,
"IDF_TOOLCHAIN": "gcc",
"IDF_TOOLCHAIN_GCC": true,
"LIBC_LOCKS_PLACE_IN_IRAM": true,
"LIBC_MISC_IN_IRAM": true,
"LIBC_NEWLIB": true,
"LIBC_NEWLIB_NANO_FORMAT": false,
"LIBC_OPTIMIZED_MISALIGNED_ACCESS": false,
"LIBC_TIME_SYSCALL_USE_HRT": false,
"LIBC_TIME_SYSCALL_USE_NONE": false,
"LIBC_TIME_SYSCALL_USE_RTC": false,
"LIBC_TIME_SYSCALL_USE_RTC_HRT": true,
"LOG_COLORS": false,
"LOG_DEFAULT_LEVEL": 3,
"LOG_DEFAULT_LEVEL_DEBUG": false,
"LOG_DEFAULT_LEVEL_ERROR": false,
"LOG_DEFAULT_LEVEL_INFO": true,
"LOG_DEFAULT_LEVEL_NONE": false,
"LOG_DEFAULT_LEVEL_VERBOSE": false,
"LOG_DEFAULT_LEVEL_WARN": false,
"LOG_DYNAMIC_LEVEL_CONTROL": true,
"LOG_IN_IRAM": true,
"LOG_MASTER_LEVEL": false,
"LOG_MAXIMUM_EQUALS_DEFAULT": true,
"LOG_MAXIMUM_LEVEL": 3,
"LOG_MAXIMUM_LEVEL_DEBUG": false,
"LOG_MAXIMUM_LEVEL_VERBOSE": false,
"LOG_MODE_TEXT": true,
"LOG_MODE_TEXT_EN": true,
"LOG_TAG_LEVEL_CACHE_ARRAY": false,
"LOG_TAG_LEVEL_CACHE_BINARY_MIN_HEAP": true,
"LOG_TAG_LEVEL_IMPL_CACHE_AND_LINKED_LIST": true,
"LOG_TAG_LEVEL_IMPL_CACHE_SIZE": 31,
"LOG_TAG_LEVEL_IMPL_LINKED_LIST": false,
"LOG_TAG_LEVEL_IMPL_NONE": false,
"LOG_TIMESTAMP_SOURCE_RTOS": true,
"LOG_TIMESTAMP_SOURCE_SYSTEM": false,
"LOG_VERSION": 1,
"LOG_VERSION_1": true,
"LOG_VERSION_2": false,
"MMU_PAGE_MODE": "64KB",
"MMU_PAGE_SIZE": 65536,
"MMU_PAGE_SIZE_64KB": true,
"PARTITION_TABLE_CUSTOM": false,
"PARTITION_TABLE_CUSTOM_FILENAME": "partitions.csv",
"PARTITION_TABLE_FILENAME": "partitions_singleapp.csv",
"PARTITION_TABLE_MD5": true,
"PARTITION_TABLE_OFFSET": 32768,
"PARTITION_TABLE_SINGLE_APP": true,
"PARTITION_TABLE_SINGLE_APP_LARGE": false,
"PARTITION_TABLE_TWO_OTA": false,
"PARTITION_TABLE_TWO_OTA_LARGE": false,
"RTC_CLK_CAL_CYCLES": 1024,
"RTC_CLK_SRC_EXT_CRYS": false,
"RTC_CLK_SRC_EXT_OSC": false,
"RTC_CLK_SRC_INT_RC": true,
"RTC_FAST_CLK_SRC_RC_FAST": true,
"RTC_FAST_CLK_SRC_XTAL": false,
"SECURE_BOOT": false,
"SECURE_BOOT_V2_ECC_SUPPORTED": true,
"SECURE_BOOT_V2_PREFERRED": true,
"SECURE_BOOT_V2_RSA_SUPPORTED": true,
"SECURE_FLASH_ENC_ENABLED": false,
"SECURE_ROM_DL_MODE_ENABLED": true,
"SECURE_SIGNED_APPS_NO_SECURE_BOOT": false,
"SOC_ADC_ATTEN_NUM": 4,
"SOC_ADC_CALIBRATION_V1_SUPPORTED": true,
"SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED": true,
"SOC_ADC_DIGI_CONTROLLER_NUM": 1,
"SOC_ADC_DIGI_DATA_BYTES_PER_CONV": 4,
"SOC_ADC_DIGI_IIR_FILTER_NUM": 2,
"SOC_ADC_DIGI_MAX_BITWIDTH": 12,
"SOC_ADC_DIGI_MIN_BITWIDTH": 12,
"SOC_ADC_DIGI_MONITOR_NUM": 2,
"SOC_ADC_DIGI_RESULT_BYTES": 4,
"SOC_ADC_DIG_CTRL_SUPPORTED": true,
"SOC_ADC_DIG_IIR_FILTER_SUPPORTED": true,
"SOC_ADC_DMA_SUPPORTED": true,
"SOC_ADC_MAX_CHANNEL_NUM": 6,
"SOC_ADC_MONITOR_SUPPORTED": true,
"SOC_ADC_PATT_LEN_MAX": 8,
"SOC_ADC_PERIPH_NUM": 1,
"SOC_ADC_RTC_MAX_BITWIDTH": 12,
"SOC_ADC_RTC_MIN_BITWIDTH": 12,
"SOC_ADC_SAMPLE_FREQ_THRES_HIGH": 83333,
"SOC_ADC_SAMPLE_FREQ_THRES_LOW": 611,
"SOC_ADC_SHARED_POWER": true,
"SOC_ADC_SUPPORTED": true,
"SOC_ADC_TEMPERATURE_SHARE_INTR": true,
"SOC_AES_GDMA": true,
"SOC_AES_SUPPORTED": true,
"SOC_AES_SUPPORT_AES_128": true,
"SOC_AES_SUPPORT_AES_256": true,
"SOC_AES_SUPPORT_DMA": true,
"SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION": true,
"SOC_AHB_GDMA_SUPPORTED": true,
"SOC_AHB_GDMA_SUPPORT_PSRAM": true,
"SOC_AHB_GDMA_VERSION": 2,
"SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE": true,
"SOC_ANA_CMPR_NUM": 1,
"SOC_ANA_CMPR_SUPPORTED": true,
"SOC_ANA_CMPR_SUPPORT_ETM": true,
"SOC_APM_CPU_APM_SUPPORTED": true,
"SOC_APM_CTRL_FILTER_SUPPORTED": true,
"SOC_APM_LP_APM0_SUPPORTED": true,
"SOC_APM_SUPPORTED": true,
"SOC_APM_SUPPORT_CTRL_CFG_LOCK": true,
"SOC_APM_SUPPORT_LP_TEE_CTRL": true,
"SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL": true,
"SOC_ASSIST_DEBUG_SUPPORTED": true,
"SOC_ASYNC_MEMCPY_SUPPORTED": true,
"SOC_BITSCRAMBLER_SUPPORTED": true,
"SOC_BLE_50_SUPPORTED": true,
"SOC_BLE_CTE_SUPPORTED": true,
"SOC_BLE_DEVICE_PRIVACY_SUPPORTED": true,
"SOC_BLE_MULTI_CONN_OPTIMIZATION": true,
"SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED": true,
"SOC_BLE_POWER_CONTROL_SUPPORTED": true,
"SOC_BLE_SUPPORTED": true,
"SOC_BOD_SUPPORTED": true,
"SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED": true,
"SOC_BRANCH_PREDICTOR_SUPPORTED": true,
"SOC_BROWNOUT_RESET_SUPPORTED": true,
"SOC_BT_SUPPORTED": true,
"SOC_CACHE_FREEZE_SUPPORTED": true,
"SOC_CACHE_WRITEBACK_SUPPORTED": true,
"SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE": true,
"SOC_CLK_LP_FAST_SUPPORT_XTAL": true,
"SOC_CLK_LP_FAST_SUPPORT_XTAL_D2": true,
"SOC_CLK_OSC_SLOW_SUPPORTED": true,
"SOC_CLK_RC_FAST_SUPPORT_CALIBRATION": true,
"SOC_CLK_TREE_SUPPORTED": true,
"SOC_CLK_XTAL32K_SUPPORTED": true,
"SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED": true,
"SOC_COEX_HW_PTI": true,
"SOC_CPU_BREAKPOINTS_NUM": 4,
"SOC_CPU_CORES_NUM": 1,
"SOC_CPU_HAS_FLEXIBLE_INTC": true,
"SOC_CPU_HAS_LOCKUP_RESET": true,
"SOC_CPU_HAS_PMA": true,
"SOC_CPU_IDRAM_SPLIT_USING_PMP": true,
"SOC_CPU_INTR_NUM": 32,
"SOC_CPU_PMP_REGION_GRANULARITY": 128,
"SOC_CPU_SUPPORT_WFE": true,
"SOC_CPU_WATCHPOINTS_NUM": 4,
"SOC_CPU_WATCHPOINT_MAX_REGION_SIZE": 256,
"SOC_CRYPTO_DPA_PROTECTION_SUPPORTED": true,
"SOC_DEDICATED_GPIO_SUPPORTED": true,
"SOC_DEDIC_GPIO_IN_CHANNELS_NUM": 8,
"SOC_DEDIC_GPIO_OUT_CHANNELS_NUM": 8,
"SOC_DEDIC_PERIPH_ALWAYS_ENABLE": true,
"SOC_DEEP_SLEEP_SUPPORTED": true,
"SOC_DIG_SIGN_SUPPORTED": true,
"SOC_DMA_CAN_ACCESS_FLASH": true,
"SOC_DS_KEY_CHECK_MAX_WAIT_US": 1100,
"SOC_DS_KEY_PARAM_MD_IV_LENGTH": 16,
"SOC_DS_SIGNATURE_MAX_BIT_LEN": 3072,
"SOC_ECC_CONSTANT_TIME_POINT_MUL": true,
"SOC_ECC_EXTENDED_MODES_SUPPORTED": true,
"SOC_ECC_SUPPORTED": true,
"SOC_ECDSA_SUPPORTED": true,
"SOC_ECDSA_SUPPORT_CURVE_P384": true,
"SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE": true,
"SOC_ECDSA_SUPPORT_EXPORT_PUBKEY": true,
"SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP": true,
"SOC_EFUSE_DIS_DIRECT_BOOT": true,
"SOC_EFUSE_DIS_ICACHE": true,
"SOC_EFUSE_DIS_PAD_JTAG": true,
"SOC_EFUSE_DIS_USB_JTAG": true,
"SOC_EFUSE_ECDSA_KEY": true,
"SOC_EFUSE_ECDSA_KEY_P192": true,
"SOC_EFUSE_ECDSA_KEY_P384": true,
"SOC_EFUSE_KEY_PURPOSE_FIELD": true,
"SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS": true,
"SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS": 3,
"SOC_EFUSE_SOFT_DIS_JTAG": true,
"SOC_EFUSE_SUPPORTED": true,
"SOC_ESP_NIMBLE_CONTROLLER": true,
"SOC_ETM_CHANNELS_PER_GROUP": 50,
"SOC_ETM_GROUPS": 1,
"SOC_ETM_SUPPORTED": true,
"SOC_ETM_SUPPORT_SLEEP_RETENTION": true,
"SOC_EXTERNAL_COEX_ADVANCE": true,
"SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN": true,
"SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX": 64,
"SOC_FLASH_ENCRYPTION_XTS_AES": true,
"SOC_FLASH_ENCRYPTION_XTS_AES_128": true,
"SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND": true,
"SOC_FLASH_ENC_SUPPORTED": true,
"SOC_GDMA_NUM_GROUPS_MAX": 1,
"SOC_GDMA_PAIRS_PER_GROUP_MAX": 3,
"SOC_GDMA_SUPPORTED": true,
"SOC_GDMA_SUPPORT_ETM": true,
"SOC_GDMA_SUPPORT_SLEEP_RETENTION": true,
"SOC_GPIO_CLOCKOUT_CHANNEL_NUM": 3,
"SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT": 7,
"SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK": 0,
"SOC_GPIO_FLEX_GLITCH_FILTER_NUM": 8,
"SOC_GPIO_IN_RANGE_MAX": 28,
"SOC_GPIO_OUT_RANGE_MAX": 28,
"SOC_GPIO_PIN_COUNT": 29,
"SOC_GPIO_PORT": 1,
"SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP": true,
"SOC_GPIO_SUPPORT_ETM": true,
"SOC_GPIO_SUPPORT_FORCE_HOLD": true,
"SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP": true,
"SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP": true,
"SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER": true,
"SOC_GPIO_SUPPORT_PIN_HYS_FILTER": true,
"SOC_GPIO_SUPPORT_RTC_INDEPENDENT": true,
"SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK": 33554304,
"SOC_GPSPI_SUPPORTED": true,
"SOC_GPTIMER_SUPPORTED": true,
"SOC_HMAC_SUPPORTED": true,
"SOC_HP_I2C_NUM": 1,
"SOC_HUK_MEM_NEEDS_RECHARGE": true,
"SOC_HUK_SUPPORTED": true,
"SOC_I2C_CMD_REG_NUM": 8,
"SOC_I2C_FIFO_LEN": 32,
"SOC_I2C_NUM": 2,
"SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE": true,
"SOC_I2C_SLAVE_SUPPORT_BROADCAST": true,
"SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS": true,
"SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH": true,
"SOC_I2C_SUPPORTED": true,
"SOC_I2C_SUPPORT_10BIT_ADDR": true,
"SOC_I2C_SUPPORT_HW_FSM_RST": true,
"SOC_I2C_SUPPORT_RTC": true,
"SOC_I2C_SUPPORT_SLAVE": true,
"SOC_I2C_SUPPORT_SLEEP_RETENTION": true,
"SOC_I2C_SUPPORT_XTAL": true,
"SOC_I2S_HW_VERSION_2": true,
"SOC_I2S_NUM": 1,
"SOC_I2S_PDM_MAX_RX_LINES": 1,
"SOC_I2S_PDM_MAX_TX_LINES": 2,
"SOC_I2S_SUPPORTED": true,
"SOC_I2S_SUPPORTS_ETM": true,
"SOC_I2S_SUPPORTS_PCM": true,
"SOC_I2S_SUPPORTS_PCM2PDM": true,
"SOC_I2S_SUPPORTS_PDM": true,
"SOC_I2S_SUPPORTS_PDM_RX": true,
"SOC_I2S_SUPPORTS_PDM_TX": true,
"SOC_I2S_SUPPORTS_PLL_F160M": true,
"SOC_I2S_SUPPORTS_PLL_F240M": true,
"SOC_I2S_SUPPORTS_TDM": true,
"SOC_I2S_SUPPORTS_TX_SYNC_CNT": true,
"SOC_I2S_SUPPORTS_XTAL": true,
"SOC_I2S_SUPPORT_SLEEP_RETENTION": true,
"SOC_I2S_TDM_FULL_DATA_WIDTH": true,
"SOC_IEEE802154_SUPPORTED": true,
"SOC_INT_CLIC_SUPPORTED": true,
"SOC_INT_HW_NESTED_SUPPORTED": true,
"SOC_KEY_MANAGER_DS_KEY_DEPLOY": true,
"SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY": true,
"SOC_KEY_MANAGER_FE_KEY_DEPLOY": true,
"SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128": true,
"SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256": true,
"SOC_KEY_MANAGER_HMAC_KEY_DEPLOY": true,
"SOC_KEY_MANAGER_SUPPORTED": true,
"SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT": true,
"SOC_LEDC_CHANNEL_NUM": 6,
"SOC_LEDC_FADE_PARAMS_BIT_WIDTH": 10,
"SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX": 16,
"SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED": true,
"SOC_LEDC_SUPPORTED": true,
"SOC_LEDC_SUPPORT_FADE_STOP": true,
"SOC_LEDC_SUPPORT_PLL_DIV_CLOCK": true,
"SOC_LEDC_SUPPORT_SLEEP_RETENTION": true,
"SOC_LEDC_SUPPORT_XTAL_CLOCK": true,
"SOC_LEDC_TIMER_BIT_WIDTH": 20,
"SOC_LEDC_TIMER_NUM": 4,
"SOC_LIGHT_SLEEP_SUPPORTED": true,
"SOC_LP_AON_SUPPORTED": true,
"SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR": true,
"SOC_LP_CORE_SUPPORTED": true,
"SOC_LP_CORE_SUPPORT_ETM": true,
"SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS": true,
"SOC_LP_I2C_FIFO_LEN": 16,
"SOC_LP_I2C_NUM": 1,
"SOC_LP_I2C_SUPPORTED": true,
"SOC_LP_IO_CLOCK_IS_INDEPENDENT": true,
"SOC_LP_PERIPHERALS_SUPPORTED": true,
"SOC_LP_TIMER_BIT_WIDTH_HI": 16,
"SOC_LP_TIMER_BIT_WIDTH_LO": 32,
"SOC_LP_TIMER_SUPPORTED": true,
"SOC_LP_UART_FIFO_LEN": 16,
"SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER": 3,
"SOC_MCPWM_CAPTURE_CLK_FROM_GROUP": true,
"SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP": true,
"SOC_MCPWM_COMPARATORS_PER_OPERATOR": 2,
"SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR": 2,
"SOC_MCPWM_GENERATORS_PER_OPERATOR": 2,
"SOC_MCPWM_GPIO_FAULTS_PER_GROUP": 3,
"SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP": 3,
"SOC_MCPWM_GROUPS": 1,
"SOC_MCPWM_OPERATORS_PER_GROUP": 3,
"SOC_MCPWM_SUPPORTED": true,
"SOC_MCPWM_SUPPORT_ETM": true,
"SOC_MCPWM_SUPPORT_EVENT_COMPARATOR": true,
"SOC_MCPWM_SUPPORT_SLEEP_RETENTION": true,
"SOC_MCPWM_SWSYNC_CAN_PROPAGATE": true,
"SOC_MCPWM_TIMERS_PER_GROUP": 3,
"SOC_MCPWM_TRIGGERS_PER_OPERATOR": 2,
"SOC_MEMSPI_IS_INDEPENDENT": true,
"SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED": true,
"SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED": true,
"SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED": true,
"SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED": true,
"SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY": true,
"SOC_MMU_DI_VADDR_SHARED": true,
"SOC_MMU_LINEAR_ADDRESS_REGION_NUM": 1,
"SOC_MMU_PERIPH_NUM": 1,
"SOC_MODEM_CLOCK_IS_INDEPENDENT": true,
"SOC_MODEM_CLOCK_SUPPORTED": true,
"SOC_MPI_MEM_BLOCKS_NUM": 4,
"SOC_MPI_OPERATIONS_NUM": 3,
"SOC_MPI_SUPPORTED": true,
"SOC_MWDT_SUPPORT_SLEEP_RETENTION": true,
"SOC_PARLIO_GROUPS": 1,
"SOC_PARLIO_RX_CLK_SUPPORT_GATING": true,
"SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT": true,
"SOC_PARLIO_RX_UNITS_PER_GROUP": 1,
"SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH": 8,
"SOC_PARLIO_SUPPORTED": true,
"SOC_PARLIO_SUPPORT_I80_LCD": true,
"SOC_PARLIO_SUPPORT_SLEEP_RETENTION": true,
"SOC_PARLIO_SUPPORT_SPI_LCD": true,
"SOC_PARLIO_TRANS_BIT_ALIGN": true,
"SOC_PARLIO_TX_CLK_SUPPORT_GATING": true,
"SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA": true,
"SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION": true,
"SOC_PARLIO_TX_UNITS_PER_GROUP": 1,
"SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH": 8,
"SOC_PAU_SUPPORTED": true,
"SOC_PCNT_CHANNELS_PER_UNIT": 2,
"SOC_PCNT_GROUPS": 1,
"SOC_PCNT_SUPPORTED": true,
"SOC_PCNT_SUPPORT_CLEAR_SIGNAL": true,
"SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE": true,
"SOC_PCNT_SUPPORT_SLEEP_RETENTION": true,
"SOC_PCNT_SUPPORT_STEP_NOTIFY": true,
"SOC_PCNT_THRES_POINT_PER_UNIT": 2,
"SOC_PCNT_UNITS_PER_GROUP": 4,
"SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT": true,
"SOC_PHY_SUPPORTED": true,
"SOC_PMU_SUPPORTED": true,
"SOC_PM_CPU_RETENTION_BY_SW": true,
"SOC_PM_MODEM_RETENTION_BY_REGDMA": true,
"SOC_PM_PAU_LINK_NUM": 5,
"SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE": true,
"SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC": 4,
"SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED": true,
"SOC_PM_RETENTION_MODULE_NUM": 32,
"SOC_PM_SUPPORTED": true,
"SOC_PM_SUPPORT_BEACON_WAKEUP": true,
"SOC_PM_SUPPORT_BT_WAKEUP": true,
"SOC_PM_SUPPORT_CPU_PD": true,
"SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY": true,
"SOC_PM_SUPPORT_EXT1_WAKEUP": true,
"SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN": true,
"SOC_PM_SUPPORT_HP_AON_PD": true,
"SOC_PM_SUPPORT_MAC_BB_PD": true,
"SOC_PM_SUPPORT_MODEM_PD": true,
"SOC_PM_SUPPORT_PMU_CLK_ICG": true,
"SOC_PM_SUPPORT_PMU_MODEM_STATE": true,
"SOC_PM_SUPPORT_RC32K_PD": true,
"SOC_PM_SUPPORT_RC_FAST_PD": true,
"SOC_PM_SUPPORT_RTC_PERIPH_PD": true,
"SOC_PM_SUPPORT_TOP_PD": true,
"SOC_PM_SUPPORT_VDDSDIO_PD": true,
"SOC_PM_SUPPORT_WIFI_WAKEUP": true,
"SOC_PM_SUPPORT_XTAL32K_PD": true,
"SOC_PM_TOP_PD_NOT_ALLOWED": true,
"SOC_PSRAM_DMA_CAPABLE": true,
"SOC_PSRAM_ENCRYPTION_XTS_AES_128": true,
"SOC_RCC_IS_INDEPENDENT": true,
"SOC_RECOVERY_BOOTLOADER_SUPPORTED": true,
"SOC_RMT_CHANNELS_PER_GROUP": 4,
"SOC_RMT_GROUPS": 1,
"SOC_RMT_MEM_WORDS_PER_CHANNEL": 48,
"SOC_RMT_RX_CANDIDATES_PER_GROUP": 2,
"SOC_RMT_SUPPORTED": true,
"SOC_RMT_SUPPORT_RX_DEMODULATION": true,
"SOC_RMT_SUPPORT_RX_PINGPONG": true,
"SOC_RMT_SUPPORT_SLEEP_RETENTION": true,
"SOC_RMT_SUPPORT_TX_ASYNC_STOP": true,
"SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY": true,
"SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP": true,
"SOC_RMT_SUPPORT_TX_LOOP_COUNT": true,
"SOC_RMT_SUPPORT_TX_SYNCHRO": true,
"SOC_RMT_SUPPORT_XTAL": true,
"SOC_RMT_TX_CANDIDATES_PER_GROUP": 2,
"SOC_RNG_BUF_CHAIN_ENTROPY_SOURCE": true,
"SOC_RNG_CLOCK_IS_INDEPENDENT": true,
"SOC_RNG_RTC_TIMER_ENTROPY_SOURCE": true,
"SOC_RNG_SUPPORTED": true,
"SOC_RSA_MAX_BIT_LEN": 3072,
"SOC_RSA_SUPPORTED": true,
"SOC_RTCIO_EDGE_WAKE_SUPPORTED": true,
"SOC_RTCIO_HOLD_SUPPORTED": true,
"SOC_RTCIO_INPUT_OUTPUT_SUPPORTED": true,
"SOC_RTCIO_PIN_COUNT": 7,
"SOC_RTCIO_WAKE_SUPPORTED": true,
"SOC_RTC_FAST_MEM_SUPPORTED": true,
"SOC_RTC_MEM_SUPPORTED": true,
"SOC_RTC_MEM_SUPPORT_SPEED_MODE_SWITCH": true,
"SOC_SDIO_SLAVE_SUPPORTED": true,
"SOC_SDM_CHANNELS_PER_GROUP": 4,
"SOC_SDM_CLK_SUPPORT_PLL_F80M": true,
"SOC_SDM_CLK_SUPPORT_XTAL": true,
"SOC_SDM_GROUPS": 1,
"SOC_SDM_SUPPORTED": true,
"SOC_SECURE_BOOT_SUPPORTED": true,
"SOC_SECURE_BOOT_V2_ECC": true,
"SOC_SECURE_BOOT_V2_RSA": true,
"SOC_SHARED_IDCACHE_SUPPORTED": true,
"SOC_SHA_DMA_MAX_BUFFER_SIZE": 3968,
"SOC_SHA_GDMA": true,
"SOC_SHA_SUPPORTED": true,
"SOC_SHA_SUPPORT_DMA": true,
"SOC_SHA_SUPPORT_RESUME": true,
"SOC_SHA_SUPPORT_SHA1": true,
"SOC_SHA_SUPPORT_SHA224": true,
"SOC_SHA_SUPPORT_SHA256": true,
"SOC_SHA_SUPPORT_SHA384": true,
"SOC_SHA_SUPPORT_SHA512": true,
"SOC_SHA_SUPPORT_SHA512_224": true,
"SOC_SHA_SUPPORT_SHA512_256": true,
"SOC_SHA_SUPPORT_SHA512_T": true,
"SOC_SPIRAM_SUPPORTED": true,
"SOC_SPIRAM_XIP_SUPPORTED": true,
"SOC_SPI_FLASH_SUPPORTED": true,
"SOC_SPI_MAXIMUM_BUFFER_SIZE": 64,
"SOC_SPI_MAX_CS_NUM": 6,
"SOC_SPI_MAX_PRE_DIVIDER": 16,
"SOC_SPI_MEM_SUPPORT_AUTO_RESUME": true,
"SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND": true,
"SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE": true,
"SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP": true,
"SOC_SPI_MEM_SUPPORT_CHECK_SUS": true,
"SOC_SPI_MEM_SUPPORT_IDLE_INTR": true,
"SOC_SPI_MEM_SUPPORT_SW_SUSPEND": true,
"SOC_SPI_MEM_SUPPORT_TIMING_TUNING": true,
"SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR": true,
"SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL": true,
"SOC_SPI_MEM_SUPPORT_WRAP": true,
"SOC_SPI_PERIPH_NUM": 2,
"SOC_SPI_SLAVE_SUPPORT_SEG_TRANS": true,
"SOC_SPI_SUPPORT_CD_SIG": true,
"SOC_SPI_SUPPORT_CLK_PLL_F160M": true,
"SOC_SPI_SUPPORT_CLK_RC_FAST": true,
"SOC_SPI_SUPPORT_CLK_XTAL": true,
"SOC_SPI_SUPPORT_CONTINUOUS_TRANS": true,
"SOC_SPI_SUPPORT_DDRCLK": true,
"SOC_SPI_SUPPORT_SLAVE_HD_VER2": true,
"SOC_SPI_SUPPORT_SLEEP_RETENTION": true,
"SOC_SUPPORTS_SECURE_DL_MODE": true,
"SOC_SUPPORT_COEXISTENCE": true,
"SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY": true,
"SOC_SYSTIMER_ALARM_MISS_COMPENSATE": true,
"SOC_SYSTIMER_ALARM_NUM": 3,
"SOC_SYSTIMER_BIT_WIDTH_HI": 20,
"SOC_SYSTIMER_BIT_WIDTH_LO": 32,
"SOC_SYSTIMER_COUNTER_NUM": 2,
"SOC_SYSTIMER_FIXED_DIVIDER": true,
"SOC_SYSTIMER_INT_LEVEL": true,
"SOC_SYSTIMER_SUPPORTED": true,
"SOC_SYSTIMER_SUPPORT_ETM": true,
"SOC_SYSTIMER_SUPPORT_RC_FAST": true,
"SOC_TEMPERATURE_SENSOR_INTR_SUPPORT": true,
"SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC": true,
"SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION": true,
"SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL": true,
"SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN": true,
"SOC_TEMP_SENSOR_SUPPORTED": true,
"SOC_TIMER_GROUPS": 2,
"SOC_TIMER_GROUP_COUNTER_BIT_WIDTH": 54,
"SOC_TIMER_GROUP_SUPPORT_RC_FAST": true,
"SOC_TIMER_GROUP_SUPPORT_XTAL": true,
"SOC_TIMER_GROUP_TIMERS_PER_GROUP": 1,
"SOC_TIMER_GROUP_TOTAL_TIMERS": 2,
"SOC_TIMER_SUPPORT_ETM": true,
"SOC_TIMER_SUPPORT_SLEEP_RETENTION": true,
"SOC_TWAI_BRP_MAX": 255,
"SOC_TWAI_BRP_MIN": 1,
"SOC_TWAI_CLK_SUPPORT_XTAL": true,
"SOC_TWAI_CONTROLLER_NUM": 2,
"SOC_TWAI_MASK_FILTER_NUM": 3,
"SOC_TWAI_RANGE_FILTER_NUM": 1,
"SOC_TWAI_SUPPORTED": true,
"SOC_TWAI_SUPPORTS_RX_STATUS": true,
"SOC_TWAI_SUPPORT_FD": true,
"SOC_TWAI_SUPPORT_TIMESTAMP": true,
"SOC_UART_BITRATE_MAX": 5000000,
"SOC_UART_FIFO_LEN": 128,
"SOC_UART_HAS_LP_UART": true,
"SOC_UART_HP_NUM": 2,
"SOC_UART_LP_NUM": 1,
"SOC_UART_NUM": 3,
"SOC_UART_SUPPORTED": true,
"SOC_UART_SUPPORT_FSM_TX_WAIT_SEND": true,
"SOC_UART_SUPPORT_PLL_F80M_CLK": true,
"SOC_UART_SUPPORT_RTC_CLK": true,
"SOC_UART_SUPPORT_SLEEP_RETENTION": true,
"SOC_UART_SUPPORT_WAKEUP_INT": true,
"SOC_UART_SUPPORT_XTAL_CLK": true,
"SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN": 5,
"SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE": true,
"SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE": true,
"SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE": true,
"SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE": true,
"SOC_UHCI_NUM": 1,
"SOC_UHCI_SUPPORTED": true,
"SOC_ULP_LP_UART_SUPPORTED": true,
"SOC_ULP_SUPPORTED": true,
"SOC_USB_SERIAL_JTAG_SUPPORTED": true,
"SOC_WDT_SUPPORTED": true,
"SOC_WIFI_CSI_SUPPORT": true,
"SOC_WIFI_FTM_SUPPORT": true,
"SOC_WIFI_GCMP_SUPPORT": true,
"SOC_WIFI_HE_SUPPORT": true,
"SOC_WIFI_HW_TSF": true,
"SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH": 12,
"SOC_WIFI_MAC_VERSION_NUM": 3,
"SOC_WIFI_MESH_SUPPORT": true,
"SOC_WIFI_NAN_SUPPORT": true,
"SOC_WIFI_SUPPORTED": true,
"SOC_WIFI_SUPPORT_5G": true,
"SOC_WIFI_WAPI_SUPPORT": true,
"SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN": true,
"SOC_XTAL_SUPPORT_40M": true,
"SOC_XTAL_SUPPORT_48M": true,
"SPI_FLASH_AUTO_SUSPEND": false,
"SPI_FLASH_BROWNOUT_RESET": true,
"SPI_FLASH_BROWNOUT_RESET_XMC": true,
"SPI_FLASH_BYPASS_BLOCK_ERASE": false,
"SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED": false,
"SPI_FLASH_DANGEROUS_WRITE_ABORTS": true,
"SPI_FLASH_DANGEROUS_WRITE_ALLOWED": false,
"SPI_FLASH_DANGEROUS_WRITE_FAILS": false,
"SPI_FLASH_ENABLE_COUNTERS": false,
"SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE": true,
"SPI_FLASH_ERASE_YIELD_DURATION_MS": 20,
"SPI_FLASH_ERASE_YIELD_TICKS": 1,
"SPI_FLASH_FORCE_ENABLE_C6_H2_SUSPEND": false,
"SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND": false,
"SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST": false,
"SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM": true,
"SPI_FLASH_ROM_DRIVER_PATCH": true,
"SPI_FLASH_ROM_IMPL": false,
"SPI_FLASH_SIZE_OVERRIDE": false,
"SPI_FLASH_SUPPORT_BOYA_CHIP": true,
"SPI_FLASH_SUPPORT_GD_CHIP": true,
"SPI_FLASH_SUPPORT_ISSI_CHIP": false,
"SPI_FLASH_SUPPORT_MXIC_CHIP": false,
"SPI_FLASH_SUPPORT_TH_CHIP": false,
"SPI_FLASH_SUPPORT_WINBOND_CHIP": false,
"SPI_FLASH_SUSPEND_TRS_VAL_US": 50,
"SPI_FLASH_SUSPEND_TSUS_VAL_US": 50,
"SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED": true,
"SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED": true,
"SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED": true,
"SPI_FLASH_VERIFY_WRITE": false,
"SPI_FLASH_WRITE_CHUNK_SIZE": 8192,
"SPI_FLASH_YIELD_DURING_ERASE": true,
"XTAL_FREQ": 0,
"XTAL_FREQ_AUTO": true
}